Field of the Invention
The present invention is related to manufacturing Integrated Circuit (IC) chips, and more particularly, to forming through silicon vias (TSV) in IC chips.
Background Description
Through silicon vias (TSV) are used for a number of Integrated Circuit (IC) chip applications. Typically, TSVs are formed by etching vias through the chip and filling the vias with metal after chip circuits and wiring are nearly complete. TSV etching requires etching vias completely through a stack of back end of line (BEOL) layers to the silicon (Si) chip surface, sometimes considered or called a hard mask open (HMO), followed by a silicon specific reactive ion etch (RIE) to etch into and through the Si substrate.
If the HMO via pattern is insufficiently opened, then a dielectric film residue remains at the bottom of the vias. This dielectric film residue acts as an etch mask at the bottom of the vias, inhibiting complete Si removal. In particular, the dielectric film residual can compromise TSV integrity causing mis-formed TSVs, e.g., during a TSV copper fill step. Mis-formed and/or shallow TSVs can be mis-shapen and lead to what is known as TSV “pistoning” when copper is annealed to form the TSVs. In particular, pistoning occurs when the metal (e.g., Cu) filled into a misformed and/or improperly filled TSVs (e.g., containing voids) shifts due to subsequent thermal processing, which often pushes upward, fracturing overlying films. Also, etching typically is not uniform across a chip or wafer. For example, the HMO via pattern may open completely towards the center of a chip, with varying levels of residue remaining in the vias around the periphery. In some cases across the chip etch depth variability may be as much as one micron (˜2%) from center-to-edge. These mis-formed TSVs and TSV variability has degraded chip yield significantly.
One approach to eliminating residue extends the HMO into the silicon, e.g., etching longer. In this approach, opening the HMO may consume significant additional resist to guarantee fully etching into the Si for edge TSVs that normally under etch. This additional resist consumption can prevent further processing, i.e., Si RIE, that may be necessary to make long extensions into the silicon. Complete removal of the resist carries the risk of etching through top field dielectric layers and copper, wires and/or vias, which would have detrimental effects on the etch chamber.
Thus, there is a need for well-formed TSVs, and more particularly, for forming a clean HMO via pattern without residual dielectric material remaining on silicon at the via bottom in the open vias.